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Intel Core 2 Extreme Processor QX9775 Δ Datasheet February 2008 Document Number: INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel Core 2 Extreme processor QX9775 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Δ Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See for details. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See for details. Intel 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for Intel 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardware and software configurations. See for more information including details on which processors support Intel 64, or consult with your system vendor for more information. Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality. ± Intel Virtualization Technology requires a computer system with an enabled Intel processor, BIOS, virtual machine monitor (VMM) and, for some uses, certain platform software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor. Not all specified units of this processor support Enhanced Intel SpeedStep Technology. See the Processor Spec Finder at / or contact your Intel representative for more information. Not all specified units of this processor support Thermal Monitor 2, Enhanced HALT State and Enhanced Intel SpeedStep Technology. See the Processor Spec Finder at or contact your Intel representative for more information. Warning: Altering clock frequency and/or voltage may (i) reduce system stability and useful life of the system and processor; (ii) cause the processor and other system components to fail; (iii) cause reductions in system performance; (iv) cause additional heat or other damage; and (v) affect system data integrity. Intel has not tested, and does not warranty, the operation of the processor beyond its specifications. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Pentium, Core, speedstep, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright 2008, Intel Corporation. 2 Datasheet Contents 1 Introduction Terminology References Electrical Specifications Front Side Bus and GTLREF Power and Ground Lands Decoupling Guidelines Front Side Bus Clock (BCLK[1:0]) and Processor Clocking Voltage Identification (VID) Reserved, Unused, and Test Signals Front Side Bus Signal Groups CMOS Asynchronous and Open Drain Asynchronous Signals Test Access Port (TAP) Connection Platform Environmental Control Interface (PECI) DC Specifications Mixing Processors Absolute Maximum and Minimum Ratings Processor DC Specifications AGTL+ FSB Specifications Mechanical Specifications Package Mechanical Drawings Processor Component Keepout Zones Package Loading Specifications Package Handling Guidelines Package Insertion Specifications Processor Mass Specifications Processor Materials Processor Markings Processor Land Coordinates Land Listing and Signal Description Land Listing Signal Definitions Thermal Specifications Package Thermal Specifications Processor Thermal Features Platform Environment Control Interface (PECI) Features Power-On Configuration Options Clock Control and Low Power States Enhanced Intel SpeedStep Technology Datasheet 3 Figures 2-1 Input Device Hysteresis Processor Load Current versus Time Processor VCC Static and Transient Tolerance Load Lines VCC Overshoot Example Waveform Differential Clock Waveform Differential Clock Crosspoint Specification Differential Rising and Falling Edge Rates Processor Package Assembly Sketch Processor Package Drawing (Sheet 1 of 3) Processor Package Drawing (Sheet 2 of 3) Processor Package Drawing (Sheet 3 of 3) Processor Top-side Markings (Example) Processor Land Coordinates, Top View Processor Land Coordinates, Bottom View Processor Thermal Profile Case Temperature (TCASE) Measurement Location Thermal Monitor 2 Frequency and Voltage Ordering Processor PECI Topology Conceptual Fan Control Diagram of PECI-based Platforms Stop Clock State Machine...86 Tables 2-1 Core Frequency to FSB Multiplier Configuration BSEL[2:0] Frequency Table Voltage Identification Definition Loadline Selection Truth Table for LL_ID[1:0] Market Segment Selection Truth Table for MS_ID[1:0] FSB Signal Groups AGTL+ Signal Description Table Non AGTL+ Signal Description Table Signal Reference Voltages PECI DC Electrical Limits Processor Absolute Maximum Ratings Voltage and Current Specifications Processor VCC Static and Transient Tolerance AGTL+ Signal Group DC Specifications CMOS Signal Input/Output Group and TAP Signal Group DC Specifications Open Drain Output Signal Group DC Specifications VCC Overshoot Specifications AGTL+ Bus Voltage Definitions FSB Differential BCLK Specifications Package Loading Specifications Package Handling Guidelines Processor Materials Land Listing by Land Name Land Listing by Land Number Signal Definitions Processor Thermal Specifications Processor Thermal Profile Table GetTemp0() GetTemp1()Error Codes Power-On Configuration Option Lands Extended HALT Maximum Power Datasheet Revision History Revision Description Date -001 Initial release February 2008 Datasheet 5 6 Datasheet Intel Core 2 Extreme Processor QX9775 Δ Features Available at 3.2 GHz FSB frequency at 1600 MHz Enhanced Intel Speedstep Technology Supports Intel 64 Φ architecture Supports Intel Virtualization Technology Supports Execute Disable Bit capability Binary compatible with applications running on previous members of the Intel microprocessor line Intel Wide Dynamic Execution Intel Advanced Smart Cache Intel Smart Memory Access Intel Intelligent Power Capability Intel Advanced Digital Media Boost Optimized for 32-bit applications running on advanced 32-bit operating systems Two 6 MB Level 2 caches Intel HD Boost utilizing new SSE4 instructions for improved multimedia performance, especially for video encoding and photo processing System Management mode 24-way cache associativity provides improved cache hit rate on load/store operations 771-land Package The Intel Core 2 Extreme processor QX9775, designed for dual-socket configurations, delivers Intel's most advanced processor for professional multimedia content creation and for intense visual gaming. The processor is designed to deliver performance across applications and usages where end-users can truly appreciate and experience the performance. Datasheet 7 8 Datasheet Introduction 1 Introduction The Intel Core 2 Extreme processor QX9775 is a server/workstation processor using four 45-nm Hi-k next generation Intel Core microarchitecture cores. The processor is manufactured on Intel s 45 nanometer process technology combining high performance with the power efficiencies of a low-power microarchitecture. The Intel Core 2 Extreme processor QX9775 maintains the tradition of compatibility with IA-32 software. Note: For this document, Intel Core 2 Extreme processor QX9775 is referred to as processor. Key processor features include on-die, primary 32-kB instruction cache and 32-kB writeback data cache in each core and 12 MB (2 x 6 MB) Level 2 cache with Intel Advanced Smart Cache Architecture. The processors Data Prefetch Logic speculatively fetches data to the L2 cache before an L1 cache requests occurs, resulting in reduced effective bus latency and improved performance. The 1600 MHz Front Side Bus (FSB) is a quadpumped bus running from a 400 MHz system clock making GBytes per second data transfer rates possible. Enhanced thermal and power management capabilities are implemented including Intel Thermal Monitor (TM1), Thermal Monitor 2 (TM2) and Enhanced Intel SpeedStep Technology. These technologies are targeted for dual processor configurations in enterprise environments. TM1 and TM2 provide efficient and effective cooling in high temperature situations. Enhanced Intel SpeedStep Technology provides power management capabilities to servers and workstations. Processor features also include Intel Wide Dynamic Execution, enhanced floating point and multi-media units, Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3), and Streaming SIMD Extensions 4.1 (SSE4.1). Advanced Dynamic Execution improves speculative execution and branch prediction internal to the processor. The floating point and multi-media units include 128-bit wide registers and a separate register for data movement. SSE3 instructions provide highly efficient double-precision floating point, SIMD integer, and memory management operations. The processor supports Intel 64 Architecture as an enhancement to Intel's IA-32 architecture. This enhancement allows the processor to execute operating systems and applications written to take advantage of the 64-bit extension technology. Further details on Intel 64 Architecture and its programming model can be found in the Intel 64 and IA-32 Architectures Software Developer s Manual, at products/processor/manuals/. In addition, the processor supports the Execute Disable Bit functionality. When used in conjunction with a supporting operating system, Execute Disable allows memory to be marked as executable or non executable. This feature can prevent some classes of viruses that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. Further details on Execute Disable can be found at The processor supports Intel Virtualization Technology for hardware-assisted virtualization within the processor. Intel Virtualization Technology is a set of hardware enhancements that can improve virtualization solutions. Intel Virtualization Technology is used in conjunction with Virtual Machine Monitor software enabling multiple, independent software environments inside a single platform. Further details on Intel Virtualization Technology can be found at platform-technology/virtualization/index.htm. Datasheet 9 Introduction The processor is intended for high performance server and workstation systems. The processor supports a Dual Independent Bus (DIB) architecture with one processor on each bus, up to two processor sockets in a system. The DIB architecture provides improved performance by allowing increased FSB speeds and bandwidth. The processor is packaged in an FC-LGA Land Grid Array package with 771 lands for improved power delivery. It uses a surface mount LGA771 socket that supports Direct Socket Loading (DSL). The Intel Core 2 Extreme processor QX9775-based platforms implement independent core voltage (V CC ) power planes for each processor. FSB termination voltage (V TT ) is shared and must connect to all FSB agents. The processor core voltage uses power delivery guidelines specified by VRM/EVRD 11.0 and its associated load line (see Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines for further details). VRM/EVRD 11.0 will support the power requirements of all frequencies of the processor. The processor supports a1600 MHz Front Side Bus operations. The FSB uses a splittransaction, deferred reply protocol and Source-Synchronous Transfer (SST) of address and data to improve performance. The processor transfers data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a doubleclocked or a 2X address bus. In addition, the Request Phase completes in one clock cycle. The FSB is also used to deliver interrupts. Signals on the FSB use Assisted Gunning Transceiver Logic (AGTL+) level voltages. Section 2.1 contains the electrical specifications of the FSB. 1.1 Terminology A # symbol after a signal name refers to an active low signal, indicating a signal is in the asserted state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the # symbol implies that the signal is inverted. For example, D[3:0] = HLHL refers to a hex A, and D[3:0]# = LHLH also refers to a hex A (H= High logic level, L= Low logic level). Commonly used terms are explained here for clarification: Intel Core 2 Extreme processor QX9775 Intel 64-bit microprocessor intended for dual processor desktops. The processor is based on Intel s 45 nanometer process, and packaged in the FC-LGA package with four processor cores. FC-LGA (Flip Chip Land Grid Array) Package The processor package is a Land Grid Array, consisting of a processor core mounted on a pinless substrate with 771 lands, and includes an integrated heat spreader (IHS). LGA771 socket The processor interfaces to the baseboard through this surface mount, 771 Land socket. See the LGA771 Socket Design Guidelines for details regarding this socket. Processor core Processor core with integrated L1 cache. L2 cache and system bus interface are shared between the two cores on the die. All AC timing and signal integrity specifications are at the pads of the system bus interface. Front Side Bus (FSB) The electrical interface that connects the processor to the chipset. Also referred to as the processor system bus or the system bus. All memory and I/O transactions, as well as interrupt messages, pass between the processor and chipset over the FSB. Dual Independent Bus (DIB) A front side bus architecture with one processor on each of several processor buses, rather than a processor bus shared between 10 Datasheet Introduction two processor agents. The DIB architecture provides improved performance by allowing increased FSB speeds and bandwidth. Functional Operation Refers to the normal operating conditions in which all processor specifications, including DC, AC, FSB, signal quality, mechanical and thermal are satisfied. Storage Conditions Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor lands should not be connected to any supply voltages, have any I/Os biased or receive any clocks. Upon exposure to free air (that is, unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material. Priority Agent The priority agent is the host bridge to the processor and is typically known as the chipset. Symmetric Agent A symmetric agent is a processor which shares the same I/O subsystem and memory array, and runs the same operating system as another processor in a system. Systems using symmetric agents are known as Symmetric Multiprocessing (SMP) systems. Integrated Heat Spreader (IHS) A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface. Thermal Design Power (TDP) Processor thermal solutions should be designed to meet this target. It is the highest expected sustainable power while running known power intensive applications. TDP is not the maximum power that the processor can dissipate. Intel 64 Architecture An enhancement to Intel's IA-32 architecture that allows the processor to execute operating systems and applications written to take advantage of the 64-bit extension technology. Enhanced Intel SpeedStep Technology Technology that provides power management capabilities to servers and workstations. Platform Environment Control Interface (PECI) A proprietary one-wire bus interface that provides a communication channel between Intel processor and external thermal monitoring devices, for use in fan speed control. PECI communicates readings from the processor s digital thermometer. PECI replaces the thermal diode available in previous processors. Intel Virtualization Technology Processor virtualization, which when used in conjunction with Virtual Machine Monitor software enables multiple, robust independent software environments inside a single platform. VRM (Voltage Regulator Module) DC-DC converter built onto a module that interfaces with a card edge socket and supplies the correct voltage and current to the processor based on the logic state of the processor VID bits. EVRD (Enterprise Voltage Regulator Down) DC-DC converter integrated onto the system board that provides the correct voltage and current to the processor based on the logic state of the processor VID bits. V CC The processor core power supply. V SS The processor ground. V TT FSB termination voltage. Datasheet 11 Introduction 1.2 References Material and concepts available in the following documents may be beneficial when reading this document. Document Intel Core 2 Extreme Processor QX9775 Specification Update Intel Core 2 Extreme Processor QX9775 Thermal and Mechanical Design Guidelines Addendum (TMDG) LGA771 Socket Mechanical Design Guide Voltage Regulator Module (VRM) and Enterprise Voltage Regulator- Down (EVRD) 11.0 Design Guidelines AP-485, Intel Processor Identification and the CPUID Instruction Intel 64 and IA-32 Intel Architecture Software Developer's Manuals Volume 1: Basic Architecture Volume 2A: Instruction Set Reference, A-M Volume 2B: Instruction Set Reference, N-Z Volume 3A: System Programming Guide Volume 3B: System Programming Guide Intel 64 and IA-32 Intel Architecture Optimization Reference Manual Intel 64 and IA-32 Intel Software Developer's Manual Documentation Changes Location design/processor/ specupdt/ htm design/processor/ designex/ htm design/xeon/guides/ htm design/processor/ applnots/ htm design/processor/ applnots/ htm products/processor/ manuals/ products/processor/ manuals/ products/processor/ manuals/ 12 Datasheet Electrical Specifications 2 Electrical Specifications 2.1 Front Side
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