A 5.4mW 0.07mm² 2.4GHz Front-End Receiver in 90nm for WPAN | Electronic Filter | Electrical Impedance

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  368ã 2008 IEEE International Solid-State Circuits Conference ISSCC 2008 / SESSION 20 / WLAN/WPAN / 20.7 20.7A 5.4mW0.07mm² 2.4GHz Front-End Receiver in 90nm CMOS for IEEE 802.15.4 WPAN Manuel Camus 1,2 , Benoit Butaye 1 , Luc Garcia 1 , Mathilde Sie 1 , Bruno Pellat 1 , Thierry Parra 2 1 STMicroelectronics, Crolles, France 2 LAAS-CNRS, Toulouse, France The aim of the 2.4GHz front-end receiver presented in this paperis the minimization of both cost and energy consumption, focusing on WPAN IEEE 802.15.4 transceivers.Itincludes the entire RFpart, from the balun to the first stage of the channel filter, as wellas the LO signal conditioning cells. The proposed architecture usesan unmatched inductorless LNA and a new clocking scheme on astandard passive mixer. Compared to previously reportedIEEE 802.15.4 receivers[1-3],an area reduction by at least 70%isachieved. The power consumption is relatively low at 5.4mW withastate-of-the-art noise and linearity performance. The receiverfront-end operates at 1.35V. It is implemented ina 90nm CMOStechnology using two thick metals, and alucap withRFMOMcapacitors. The receiver block diagram is shown in Fig.20.7.1.It is based ona 6MHz low-IF topologywhich leads to 30dB rejection of IEEE802.11b interferers when a 34dB image-rejection third-orderpolyphase channel filter is implemented. Special attention hasbeen paid topower consumption and cost reduction by minimizing the area and the number of external components. To this aim,thereceiver uses an integrated balun with a 50 Ω input and two differ-ential 100 Ω and 200 Ω output ports,in order to optimize both theRX noise figure and the TX output power. It also uses an inductor-less LNA with a high input impedance, a low-losspassive mixerand a LO divide-by-two with lowdynamic-current latches. In thisdesign, only the first stage of the channel filter is implemented,which consists of a 3MHz-bandwidth active-RC polyphase filter,reaching 35dBv/dBm of total receiver gain. A 1 st -order 400kHzhigh-pass filter is added before the filter for DC-offset suppression.Resulting gain and NF measured frequency responses are shownin Fig. 20.7.2.The low gain of the single-stage LNA (14dB) is compensated by set-ting ahigh input impedance value for the receiver. Since no imped-ance matching is used between the antenna and the LNA, the volt-age magnitude at the LNA input can be up to twice as large, ascompared to that of areceiver with input matching. Of course, thisprinciple makes the receiver performance more sensitive to thepackage and board implementation. Nevertheless, if there is noimpedance mismatch between the antenna and its connection line,the voltage at the LNA input remains maximum whatever the linelength is. As a limit, series resistances of the integrated balunreduce the parallel receiver input impedance, resulting in a finalmeasured extra gain value of 3.9dB instead of the 6dB value theo-retically expected.This extra gain prior to the LNA improves theoverall noise figure of the receiver (Fig. 20.7.2).The LNA uses a cascaded pseudo-differential structure with resis-tive loads(Fig. 20.7.3). A control loop maintains its biascurrentat1.2mA,reducing its sensitivityversus supply and process varia-tions. To meet gain specifications,the LNA is loaded witha highvalue resistor (R L =800 Ω ). An output buffer realizes aninterfacewith the mixer (Fig. 20.7.3). This buffer draws 500µA, has a con-stant 4dB gainand sets the IIP3 to −10dBm at the receiver input.The buffer transistor sizes are chosen relatively small so as not toimpact the LNA bandwidth while maintaining good noise perform-ance. Moreover, for the purpose of mixer image rejection, the splitof the signal into I and Q channelscannot be done with two buffersbecause of matching. For this reason, the receiver consists of onlyone buffer and the split is realized with seriescapacitors (Fig.20.7.1). The passive mixer(Fig. 20.7.4) is implemented with four switches(W=5µm), and operates like a voltage conveyor. A mixer driven bya classical square-wave LO presents losses (about 4dB) due toaveraging of half a period of a sinusoidal wave (Fig. 20.7.4).Moreover, due to the ratio between the high output impedance of the buffer and the mixer series resistance, an additional 4dBattenuation will occur, because of interactions between I and Qchannels. The proposed solution thus usesthe voltage output of acapacitatively loaded mixer whosesquare-wave LO duty cycle islower than 1/4. Since there is no longer a commutation of Ichan-nel when the Q switch is ON, or vice versa, there is no longer inter-action between channels. Moreover, the averaging window isreduced and the mixer peak output voltage becomes close to itspeak input voltage(Fig. 20.7.4). A¼-duty-cycle square-wave LOtherefore reducestotallosses from 8 downto 1.2dB. The passivemixer linearity is a function of the time it takes for the switchimpedance to vary. By keeping LO slopes steep enough,the linear-ity is unchanged.The LO path is composed of a divide-by-two,which generates sig-nals in quadrature, a buffer and NOR gates settingthe ¼ dutycycle. The divider involves two dynamic latches(Fig. 20.7.5), whichare built-up by two inverters, two memory cells and only twoswitches. Compared to a classical solution, this topology presentsimproved differential performance and tolerates lower input signallevels. By reducing transistor sizes, the divider is optimized forsmall dynamic current draw. However, because it is part of theimage-rejection budget, the I/Q phase mismatch limits this reduc-tion. Monte-Carlo simulations gives 2°phase mismatch at 3 σ  ,whilethe LO path draws 1mA. A voltage conveyormixer operation needs a high input impedancechannel filter. Moreover, because the LNA and the mixer exhibitlimited gain values (less than 17dB for the combination), a low-noise first stage has been designed for the channel filter (inputnoise<12nV/   √  Hz). The proposed solution uses two single-endedopamps(Fig. 20.7.1). It presents the best trade-off between inputimpedance value, noise and linearity performance. A value of 350MHz of GBW is reached for a800µA current draw, which is suf-ficient to realize a 6MHz polyphase filter. Five calibration bits areused on the capacitive resonator, in order to compensate both tem-perature and process variations.Three gain steps of 6dB areimplemented just before the channel filter by means of resistivedividers. The chip is fabricated in a 90nm CMOS process. A die micrographis shown in Fig. 20.7.7. In addition to Fig. 20.7.2, Fig. 20.7.6sum-marizes measurements performed on the receiver with and with-out an input integrated balun. Performanceresults are de-embed-ded at the chip input and the resultsare averagedover12 dies.Compared to previously reported IEEE802.15.4 front-endreceivers, this work presents favorable trade-off between noise,linearity and power consumption. Moreover, the main improve-ment remainsthe area reduction, sincethe receiver front-end areais 0.07mm²,and 0.23mm² when the input balun is integrated onchip.  References: [1] I.Nam, K.Choi, J.Lee et al., “A 2.4GHz Low-Power Low-IF Receiver andDirect-Conversion Transmitter in 0.18-µm CMOS for IEEE 802.15.4 WPAN Applications,”  IEEE Trans.Microwave Theory and Techniques , vol. 55,no. 4,pp. 682-689, Apr.2007.[2] W.Kluge, F. Poegel, H. Roller et al.,“A Fully Integrated 2.4GHz IEEE802.15.4-Compliant Transceiver for ZigBee Applications,“  IEEE ISSCC Dig.Tech. Papers , pp. 372-373, Feb. 2006.[3] T.-K.Nguyen, V. Krizhanovskii, J. Lee et al., “A Low-Power RF Direct-Conversion Receiver/Transmitter for 2.4-GHz-Band IEEE 802.15.4Standard in 0.18-µm CMOS Technology,”  IEEE Trans. Microwave Theoryand Techniques , vol. 54, no. 12, pp. 4062-4071, Dec. 2006. 978-1-4244-2011-7/08/$25.00 ©2008 IEEE  Please click on paper title to view Visual Supplement.  Please click on paper title to view a Visual Supplement.  369DIGEST OF TECHNICAL PAPERS ã Continued on Page 620 ISSCC 2008 / February 5, 2008 / 4:45 PM Figure 20.7.1: Receiver block diagram.Figure 20.7.2: Measured front-end receiver frequency and noise responses. Figure 20.7.3: LNA and Buffer Schematics. Figure 20.7.5: Divider-by-two and latch schematics . Figure 20.7.6: Measurement results and performance comparison of 2.4GHz IEEE802.15.4 front-end receivers.Figure 20.7.4: Passive-mixer schematic and transient signals versus LO duty cycle,when LO and RF have the same frequency and are in phase. 42 π 2  + π   2 This work  W/ Balun This work  W/O Balun [1][2][3]Gain  35dB/dBm 37dB/dBm NA NA 40dB/dBm NF 7.5dB 6dB <10dB 5.7dB 7.3dB IIP3  − 10dBm  − 12dBm  − 15dBm  − 16dBm  − 8dBm ICP1  − 18dBm  − 20dBm NA NA  − 18dBm IR   >32dB >32dB >35dB 34dB NA CurrentSupply Power 4mA1.35V5.4mW4mA1.35V5.4mW5mA1.8V9mW4.5mA1.8V8.1mW3.5mA * 1.8V6.3mW * ProcessArea 90nm CMOS 0.23mm² 90nm CMOS 0.07mm² 0.18µm CMOS 0.5mm² 0.18µm CMOS 0.3mm² 0.18µm CMOS 1.8mm² * Current draw does not include divider-by-two and LO buffers. 20  Please click on paper title to view Visual Supplement.  Please click on paper title to view a Visual Supplement.  620ã 2008 IEEE International Solid-State Circuits Conference978-1-4244-2011-7/08/$25.00 ©2008 IEEE ISSCC 2008 PAPER CONTINUATIONS Figure 20.7.7: Die Micrograph of the test chip in 90nm CMOS.  Please click on paper title to view Visual Supplement.  Please click on paper title to view a Visual Supplement.
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