A 5.3 GHz Programmable Divider for HiPerLAN in 0.25µm CMOS - PDF

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A 5.3 GHz Programmable Divider for HiPerLAN in 0.25µm CMOS N. Krishnapura 1 & P. Kinget 2 Lucent Technologies, Bell Laboratories, USA. 1 Currently at Columbia University, New York, NY, 10027, USA. 2 Currently

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A 5.3 GHz Programmable Divider for HiPerLAN in 0.25µm CMOS N. Krishnapura 1 & P. Kinget 2 Lucent Technologies, Bell Laboratories, USA. 1 Currently at Columbia University, New York, NY, 10027, USA. 2 Currently at Broadcom, Irvine, CA, USA. Programmable divider for a HiPerLAN carrier synthesizer(5 channels) f ref MHz phase detector loop filter VCO D f ref Low 0.25µm CMOS (~ 1.8V) Programmability D: {220, 224} D f in = D f ref high input frequency ( GHz) ~ 300 mv pk (~ 0 dbm) Divider architecture: Outline Phase switching. Timing issues. Solution: Signal retiming. Circuit implementation: High speed 2(D-Flip Flop) stage. Measurement results. Comparison & conclusions. f in /2 Phase switching divider 5.3 GHz 2.6 GHz 1.3 GHz 23 MHz f in /2 f in /4 f in /(4N+K) 0 o 90 o 180 o 270 o MUX pulse width = 4T in or 5T in /N rising edges separated by one input cycle [Craninckx, JSSC 96] DECODER 4 STATE MACHINE K pulses per output cycle PULSE GENERATOR Division factor D K phase switches per output cycle: (4N + K) + No high speed feedback loops around multiple flip-flops. Glitches Retiming f in 1/4 f in X Y X Y correct SY OUT elongated pulse incorrect SY OUT spurious pulse 4 T in 5 T in 4 T in 4 T in SY YON OUT modified control timing 5 T in Change clocks only when both clocks are in the same state. Phase switching divider with retiming retimed clocks and controls f in /2 f in /2 0 o 90 o 180 o 270 o RETIMER MUX /N f in /(4N+K) rising edges separated by 1 input cycle un-synchronized control signals DECODER 4 STATE MACHINE K pulses per output cycle PULSE GENERATOR Division factor D Retimer inserted after the second stage: enforces control timing. Retimer: Implementation clocks unsynchronized control signal X Y SY YON synchronized clock & control to MUX clock buffer with same delay as the control generator Y CY 0 New control generated when both clocks are high. Clock and control go through identical stages. Feedforward operation for high speed. High speed 2 stages / latches pmos in signal path (TSPC) OUT stacked devices too little headroom D D B D D I bias (Razavi 95) (source coupled logic) Goals: Low (1.8 V) & high speed(5.5 GHz) pmos: much smaller drive than nmos. Pseudo-nMOS low voltage latch D D 0.25µm CMOS, = 1.8 V: 3 stage ring osc. CMOS: 2.8 GHz. pseudo-nmos: 6 GHz. B 5.5 GHz 2 stage B B 0 o 180 o input ac coupling B B 5.5 GHz 2 with 300mV pk (SE) inputs at = 1.8V. Disabled by pulling, B inputs to the rails. Programmable divider 0 o f in f in /2 /2 RETIMER /2 90 o 180 o 270 o MUX /3 /3 /3 f in /(216+K) DECODER 4 STATE MACHINE PULSE GENERATOR 4 to 8 pulses per output cycle Division factor D {220,, 224} = {4,,8} = {4,,8} 3 stages: similar to 2, with gated input branches. 3 stage LOGIC IMPLEMENTATION D D f clk /3 f 2 clk D 1 D B differential realization D 1 D 2 D 1 B D 2 B AND gate: combined with the DFF input branches. Chip Photograph o/p buffer inp out divider ~0.09 mm 2 gnd inn last 4 stages 1 st 2 2 nd 2 retimer other logic ckts. Measurements: Sensitivity = 1.8V = 2.0V = 2.2V = 1.8V = 2.2V V i, pk (SE) / V V i, pk (SE) / V f / GHz f / GHz 5.5 GHz operation with = 2.2 V, 300mV pk (SE) input. Changed technology: major discrepancy between models and process. Phase noise measurement setup clock DIVIDER 1 PHASE SHIFT 90 o PHASE DETECTOR SPECTRUM ANALYZER DIVIDER 2 SIGNAL ANALYZER HP PHASE NOISE MEASUREMENT SYSTEM(HP 3048) Divider contributes phase noise inside the loop bandwidth. Measured noise = twice the noise of each divider. Input referred phase 5.5 GHz): + 47dB (220x). Measurements: Phase Noise o/p phase noise from 2 dividers & o/p buffers. ~ khz offset. 1/f behavior down to 1Hz. Summary Technology 0.25 µm CMOS Chip Area 0.09 mm 2 I( ) f in, max Sensitivity o/p phase noise (5.5 GHz signal i/p) I( ) f in, max Sensitivity o/p phase noise (4.5 GHz signal i/p) 2.2 V 37 ma 5.5 GHz 300 mv pk., SE -131 dbc / 1 khz 1.8 V 24 ma 4.5 GHz 300 mv pk., SE -133 dbc / 1 khz Comparison of CMOS dividers This work Tech. f in, max GHz V P d mw Input V pk Phase Noise (input ref.) 0.25 µm De Muer 98 8/9 0.7 µm Kurizu µm Craninckx µm Razavi µm Foroudi µm H. Cong 88 4/5 0.4 µm Maeda µm GaAs Conclusions Programmable divider for HiPerLAN in CMOS. Retiming circuit for reliable phase switching. 5.5 GHz low voltage 2 stage in 0.25µm CMOS. Low phase noise achieved at a high input frequency. Acknowledgments W. Fischer for layout, V. Boccuzzi for testing. A. Dunlop, M. Banu, R. Melville, H. Wang for test equipment and support.
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